In ULSI fabrication processes of electronic devices (technological processes whose minimum planar definition width is less than 0.5 .mu.m), containment of the lateral dimensions of the features that define the various integrated structures becomes more and more complex and difficult to obtain though even more important to guarantee. To achieve this, there is a need for the ability to maintain an adequate electrical insulation between two adjacent elements in the device layout. The electrical insulation substantially depends on two factors:
1) The selective growth/deposition of an oxide (for example, the LOCOS technique), able to define adjacent areas on the silicon, separated by a field oxide, where the integrated structures of distinct active circuit elements, e.g. transistors, memory cells, etc., will be formed; and PA1 2) The doping processes of active areas of the silicon semiconductor substrate, applied via ion implantation, to form insulating junctions electrically decoupling adjacent circuit elements even in the presence of strong bias voltages. PA1 1) a scattering phenomena with the nuclei of the atoms of the field oxide (nuclear scattering); and PA1 2) a scattering phenomena with the electrons of the atoms of the field oxide (electronic scattering).
In conventional fabrication processes (minimum planar definition width &gt;0.5 .mu.m), the doping process occurs by relatively low kinetic energy ion implantation (ion acceleration energies lower than 200 keV). Accordingly, the doping agents (commonly boron, phosphorus and arsenic in doses of about 10.sup.12 atom/cm.sup.2 and 5.times.10.sup.13 atom/cm.sup.2) are implanted just below the surface of the silicon substrate to a depth of few tenths of millimeters. Therefore, the formation of well regions occurs through relatively long thermal diffusion treatments in an oven at temperatures ranging between 900.degree. C. to 1200.degree. C. for 60 to 600 minutes.
This long thermal treatment may cause the diffusion of superficially implanted dopants around the implanted zone. FIGS. 1A and 1B depict this traditional process. In order to obtain a greater planar density of the circuit elements, such a process cannot be used because the long heat treatments required to diffuse the dopants to a sufficient depth also cause an intolerable lateral diffusion of dopants.
To limit such lateral diffusion of dopants, a high-energy ion implantation technique (implantation energies of 200 keV to 3000 keV) is used which permits implantation of dopant atoms at a desired depth. With this technique, it is possible to implant the same doping agents (boron, phosphorous and arsenic) in the same doses (10.sup.12 /cm.sup.2 and 5.times.10.sup.13 /cm.sup.2) employing acceleration energies that may be varied generally between 200 keV and 3000 keV. Thus, it is possible to avoid and totally eliminate the long thermal treatments that were needed to diffuse the dopants according to the conventional process.
These high-energy implantations are usually accomplished after defining the active areas, that is, after the growth/deposition of the field oxide over the separation zones among adjacent active areas on the surface of the semiconductor silicon wafer. The typical range of depth of implantation of dopant atoms into the silicon according to these high-energy processes is between 0.5 .mu.m and 4 .mu.m. According to these techniques, it is therefore inevitable that the accelerated ions cross regions covered with the field oxide, usually SiO.sub.2, whose thickness may range between 0.3 .mu.m and 0.7 .mu.m.
During the implantation process, the high-energy ions undergo collisions that slow down their speed when crossing the field oxide. The causes of this slowing down are substantially the following:
Under typical implantation conditions, only electronic scattering is active in the slowing down of the ions being implanted. Electronic scattering damages the oxide by causing the breaking of Si-O-Si chemical bonds. This type of damage had never been noticed in CMOS fabrication processes until the advent of the high-energy implantation technique. Also, this damage makes the oxide more sensitive to the wet and dry etching treatments that are normally performed after implanting dopants according to normal fabrication processing.
In particular, there are certain high energy ion implantation conditions, for example phosphorus implanted at energies higher than 2000 keV, in doses larger than 5.times.10.sup.12 atoms/cm.sup.2, according to a well known "triple well" fabrication process, which induce a remarkable increment of the oxide etch rate of about 200% as compared to a non-implanted oxide (=100%). In other words, the etch sensitivity of the oxide may double. Moreover, since these high energy implants are normally done through the apertures of photoresist masks, to allow for a selective doping of certain active areas of the device, the field oxide of the regions exposed to implantation will become more sensitive to etching than in nonexposed (masked) regions. When carrying out successive wet and/or dry etchings, as normally envisaged in a typical CMOS fabrication process, the field oxide over implanted regions will be overetched compared to the field oxide over non-implanted regions.
Another consequence is an excessive broadening of active areas delimited by the edges of the field oxide, which is accentuated by the isotropicity of wet etchings, that tend to "wear out" the often acute corners, of the field oxide edges. The result is that, in the oxide regions damaged by the ion implantation, the active areas will become wider than the design width and active areas will be closer (due to the reduction of the planar width of the field oxide). Moreover, the field oxide thickness will be reduced by the overetch effect, as illustrated in FIGS. 2A-2C. All these effects reduce isolation of the field oxide; thereby, making it inadequate.